/**
  ETFDAQ Project
  \brief Registers and ROM of a general CAEN card
  \author SUN Yazhou, asia.rabbit@163.com
  \since 2024-08-13
  \date 2024-08-13 last modified

  \copyright Copyright (c) 2024 IMP-CAS with LGPLv3 LICENSE
*/

#ifndef caen_reg_h
#define caen_reg_h

// control and data registers -- generally true, yet quite a few exceptions do exist
struct caenreg{
  static constexpr uint16_t Buffer =             0x0000; // ~0x0FFF, 4096B
  static constexpr uint16_t FirmwareRev =        0x1000;
  static constexpr uint16_t GeoAddress =         0x1002;
  static constexpr uint16_t MSCTAddress =        0x1004;
  static constexpr uint16_t BitSet1 =            0x1006;
  static constexpr uint16_t BitClear1 =          0x1008;
  static constexpr uint16_t InterruptLevel =     0x100a;
  static constexpr uint16_t InterruptVector =    0x100c;
  static constexpr uint16_t Status1 =            0x100e;
  static constexpr uint16_t Control1 =           0x1010;
  static constexpr uint16_t HighAddress =        0x1012;
  static constexpr uint16_t LowAddress =         0x1014;
  static constexpr uint16_t Reset =              0x1016;
  static constexpr uint16_t pad1 =               0x1018;
  static constexpr uint16_t MSCTControl =        0x101a;
  static constexpr uint16_t pad2 =               0x101c;
  static constexpr uint16_t pad3 =               0x101e;
  static constexpr uint16_t EventTrigger =       0x1020;
  static constexpr uint16_t Status2 =            0x1022;
  static constexpr uint16_t EventCounterLow =    0x1024;
  static constexpr uint16_t EventCounterHigh =   0x1026;
  static constexpr uint16_t IncrementEvent =     0x1028;
  static constexpr uint16_t IncrementOffset =    0x102a;
  static constexpr uint16_t LoadTestRegister =   0x102c;
  static constexpr uint16_t FCLRWindow =         0x102e;
  static constexpr uint16_t pad4 =               0x1030;
  static constexpr uint16_t BitSet2 =            0x1032;
  static constexpr uint16_t BitClear2 =          0x1034;
  static constexpr uint16_t WMemoryTestAddress = 0x1036;
  static constexpr uint16_t MemoryTestHigh =     0x1038;
  static constexpr uint16_t MemoryTestLow =      0x103a;
  static constexpr uint16_t CrateSelect =        0x103c;
  static constexpr uint16_t TestEventWrite =     0x103e;
  static constexpr uint16_t EventCounterReset =  0x1040;
  static constexpr uint16_t pad5 =               0x1042; // ~0x105f, 15 shorts
  static constexpr uint16_t TDCRange =           0x1060;
  static constexpr uint16_t Iped =               0x1060; // for qdcs
  static constexpr uint16_t pad7 =               0x1062;
  static constexpr uint16_t RMemoryTestAddress = 0x1064;
  static constexpr uint16_t pad8 =               0x1066;
  static constexpr uint16_t SWComm =             0x1068;
  static constexpr uint16_t SlideConstant =      0x106a;
  static constexpr uint16_t pad9 =               0x106c;
  static constexpr uint16_t pad10 =              0x106e;
  static constexpr uint16_t AAD =                0x1070;
  static constexpr uint16_t BAD =                0x1072;
  static constexpr uint16_t pad11 =              0x1074; // ~0x107f, 6 shorts
  static constexpr uint16_t Thresholds =         0x1080; // ~0x10bf, 32 shorts
};

/////////// following are the masks of some registers /////////////////
struct caenmask{
  //--- Control1 register ---///
  static constexpr uint16_t BERR_EN = 0x20; // enable berr in blt
  static constexpr uint16_t BLKEND = 0x20; // enable berr in blt
  // the 9-th bit in threshold, 1 to disable the channel
  static constexpr uint16_t KILLBIT = 0x100; // 1: disable the ch
  ///--- Status1 register ---///
  static constexpr uint16_t AMNESIA = 0x10; // 1: forget geo, 0: using geo from jaux
  static constexpr uint16_t DRDY = 0x1; // data ready bit
  ///--- BitSet1 register ---///
  static constexpr uint16_t SOFTRESET = 0x80; // soft ware reset bit
  ///--- BitSet2 register ---///
  static constexpr uint16_t STEPTH = 0x100; // 1: large thre steps
  static constexpr uint16_t EMPTYEN = 0x1000; // 1: enable recording of empty events
  static constexpr uint16_t OVERANGEEN = 0x8; // over-range enable bit
  static constexpr uint16_t LOWTHREEN = 0x10; // low-threshold enable bit
  static constexpr uint16_t CLRDATA = 0x4; // clear data bit
  static constexpr uint16_t ALLTRIG = 0x4000; // evCnt++ on 0: acptd trig, 1: all trig
};


// read-only memory, storing card info
struct caenrom{
  static constexpr uint16_t pad1 =        0x8000; // ~0x8025, 19 shorts
  static constexpr uint16_t OUIMSB =      0x8026; // IEEE OUI
  static constexpr uint16_t pad2 =        0x8028;
  static constexpr uint16_t OUI =         0x802a; // manufacturer identifier
  static constexpr uint16_t pad3 =        0x802c;
  static constexpr uint16_t OUILSB =      0x802e;
  static constexpr uint16_t pad4 =        0x8030;
  static constexpr uint16_t Version =     0x8032; // purchased version
  static constexpr uint16_t pad5 =        0x8034;
  static constexpr uint16_t BoardIdMSB =  0x8036;
  static constexpr uint16_t pad6 =        0x8038;
  static constexpr uint16_t BoardId =     0x803a;
  static constexpr uint16_t pad7 =        0x803c;
  static constexpr uint16_t BoardIdLSB =  0x803e;
  static constexpr uint16_t pad8 =        0x8040; // ~0x804d, 7 shorts
  static constexpr uint16_t Revision =    0x804e; // hardware revision identifier
  static constexpr uint16_t pad9 =        0x8050; // ~0x80ff, 88 shorts
  static constexpr uint16_t pad10 =       0x8100; // ~0x8eff, 1792 shorts
  static constexpr uint16_t pad11 =       0x8f00;
  static constexpr uint16_t SerialMSB =   0x8f02;
  static constexpr uint16_t pad12 =       0x8f04;
  static constexpr uint16_t SerialLSB =   0x8f06;
};

#endif
